First In First Out Memories (FIFOs) provide an important data buffer function for reading and writing operations between two discrete machines of widely differing operating frequency. FIFOs allow asynchronous operation between the two machines, wherein data can be simultaneously written to the FIFO and read therefrom. The heart of the FIFO is a dual-port memory that enables the Read and Write operations to be independent of each other, this allowing truly asynchronous operation of the input and the output.
The dual-port memory portion of the FIFO can be realized with a dual-port RAM cell that has a plurality of addressable locations. The Read and Write pointers are provided for generating the addresses of the addressable locations for the Read and Write operations, respectively. The Read and Write pointers are incremented for a Read and Write operation, respectively, instead of actually moving the data through a series of shift registers. However, it is important that the Read pointer and Write pointer do not point to the same address at the same time wherein information would be written into a memory location and read from the same memory location simultaneously. To prevent this happening, status flags are utilized to provide an indication to the user of the proximity of the two pointers.
The status flags are utilized on the Read side to indicate to the user that the FIFO is empty. In this manner, the user would not attempt to read a FIFO that is empty and, in fact, circuitry is provided to inhibit incrementing of the Read pointer to overtake the Write pointer address. In a similar manner, a full flag is provided to indicate to the user that the memory is full, such that the user will not attempt to write data to the memory or increment the pointer past the Read pointer. The full and empty status flags are conventional flags that are provided in FIFOs.
An additional flag that has been provided for FIFOs in the past is a half-full flag that indicates to the Write side of the FIFO that the FIFO is half-full and to the Read side of the FIFO that the FIFO is half-empty. However, this type of flag has some synchronization problems associated therewith, especially when utilized with asynchronous operation. For example, when data is being written into the memory at a location that will set the half-full flag to the half-full position, it is important to insure that a simultaneous Read operation does not result in a flag error wherein the flag is in the wrong state. Typically, a FIFO having 2048 registers would have the half-full flag set when data is written into the 1025th location.
To solve the problem of half-full flag errors, various FIFOs have required the use of external circuitry to insure that the Read and Write operations do not occur within a predetermined time. This typically requires a blanking circuit of some type between the Read port and the Write port to insure that the Read and/or Write operation is delayed with respect to the other. However, the main disadvantage to this is that a truly asynchronous operation is defeated and the Read and Write ports must be synchronized.